| Course Week |
Dates |
Lectures |
Assigned Text |
Lab Assignment |
Comments |
| Week 1 |
1/13/09 |
Numbers, Two's Complement |
1.1-1.4 |
Lab 1 (Intro) |
|
| |
1/15/09 |
Combinational Logic
Introduction |
1.5, 2.1 |
|
|
| Week 2 |
1/20/09 |
Combinational Logic
Basics |
2.2, 2.7 |
Lab 1 (Intro) |
|
| |
1/22/09 |
Working with K-maps |
2.7 |
|
|
| Week 3 |
1/27/09 |
K-maps and Don't
Cares |
2.4, 2.7 |
Lab 2 (7 Segment Lab) |
|
|
|
1/29/09 |
Schematics and more advanced K-maps with espresso/QM |
2.4 |
|
|
| Week 4 |
2/3/09 |
Boolean Algebra, Pushing Bubbles |
2.3, 2.5 |
Lab 2 (7 Segment Lab) |
Handout on Boolean
Algebra |
| |
2/5/09 |
Multiplexors,
Glitches, Delays, Synchronization with Clocks |
2.8.1, 2.9 |
|
|
| Week 5 |
2/10/09 |
Introduction to Sequential Logic |
3.1, 3.3 |
Lab 2a (Ring Oscillator Lab) |
|
| |
2/12/09 |
Sequential Circuits,
Finite State Machines, Moore Machines |
3.4, 2.8.2 |
|
|
| Week 6 |
2/17/09 |
Mealy Machines, Differences between Moore and Mealy |
3.4 |
Lab 3 (Sequential Logic Lab) |
|
| |
2/19/09 |
Bistable Elements,
Memory, Latches, Flip-Flops |
3.2 |
|
|
|
Week 7 |
2/24/09 |
Test I |
|
Lab 3 (Sequential Logic Lab) |
|
| |
2/26/09 |
Introduction to Hardware Descriptive
Languages, Testbenches |
4.1, 4.4, 4.5
4.6 |
|
|
| Week 8 |
3/3/09 |
HDL basics and
advanced features of simulation |
4.2, 4.3 |
Lab 4 (Tbird Lights) |
|
| |
3/5/09 |
Digital Building Blocks, Arithmetic Logic Unites, |
5.1, 5.2 |
|
|
| Week 9 |
3/10/09 |
Sequential Building
Blocks |
5.4,5.6 |
Lab 4 (Tbird Lights) |
|
| |
3/12/09 |
Logic Arrays, Field Programmable Gate Arrays (FPGAs) |
5.5 |
|
|
| Week
10 |
3/24/09 |
Memory |
5.6, 8.1 |
Lab 5 (ALU Lab - Higher Level
Combinational Logic with HDLs) |
|
| |
3/26/09 |
Project Definition,
Architecture |
handout |
|
|
| Week 11 |
3/31/09 |
Instructions/Encoding |
6.2, 5.3 |
Lab 5 (ALU Lab - Higher Level
Combinational Logic with HDLs) |
Demo |
| |
4/2/09 |
Digital Video, Color Burst |
handout |
|
|
| Week 12 |
4/7/09 |
Terminations |
Appendix A |
Project Part I |
|
| |
4/9/09 |
Combinational Logic Timing, Logic Families |
2.8,
2.9 |
|
|
| Week 13 |
4/14/09 |
Sequential Logic
Timing I |
3.5 |
Project Part I/II |
|
|
|
4/16/09 |
Test II |
|
|
|
| Week 14 |
4/21/09 |
Sequential Logic
Timing II, Setup and Hold delays, Measuring Setup/Hold. |
3.5, 3.6 |
Project Part II |
|
| |
4/23/09 |
Setup/Hold Delays, Clock Skew |
handout |
|
|
| Week 15 |
4/28/09 |
State Machine Optimization |
|
ECEN Design Day |
|
| |
4/30/09 |
Decomposition |
3.4.4 |
|
|
| |
5/1/09 |
Final Lab Report Due
(no exceptions) |
|
|
|
