//-------------------------------------------------------------
// top.v
// David_Harris@hmc.edu 9 November 2005
// Top level system including MIPS and memories
// Modified by Harsha Choday and Jun Chen
// Significant Contribution to Pac-Man code by Aaron Arneson
//-------------------------------------------------------------

module top (input clk2, reset,
	    input up, right, down, left,
	    output red_o, green_o, blue_o, hsync, vsync);
   
   wire [31:0]	pc, instr, readdata, rda, data;
   wire [31:0]	writedata, dataadr; 
   wire [31:0] dinb, dmem_data;
   wire [3:0] 	direction;
	wire  memwrite;
	wire web;

	
	// clock div by 2
	reg clk;
	initial
		begin
		clk <= 1'b0;
		end
		
	always @ (posedge clk2)
		clk <= ~clk;
		
	   
   // instantiate processor and memories
   mips mips(clk, reset, pc, instr, memwrite, dataadr, writedata, readdata);

   
	// Instruction memory
   imem imem (.a(pc[8:2]), .spo(instr));
	
	
	
	// Data memory
	dmem_2p dmem (
		.clka(clk),
		.dina(writedata), // Bus [31 : 0] 
		.addra(dataadr[12:0]), // Bus [12 : 0] 
		.wea(memwrite), // Bus [0 : 0] 
		.douta(dmem_data), // Bus [31 : 0] 
		.clkb(clk),
		.dinb(dinb), // Bus [31 : 0] 
		.addrb(rda), // Bus [12 : 0] 
		.web(web), // Bus [0 : 0] 
		.doutb(data)); // Bus [31 : 0] 

	// Dummy data input to Port-B of Dmem
	// Write enable (web) is always low  (Port-B is read only for VGA driver)
	assign web = 1'b0;
	assign dinb = 32'b0;


   // Video display driver interface
   vga vga(red_o, green_o, blue_o, hsync, vsync, rda, clk, reset, data);


   // Joystick interface
   joystick jstk(reset, up, right, down, left, direction);   
   mux2 #(32) mxd(dmem_data, {28'b0,direction}, dataadr[15], readdata);
   
endmodule // top