Laboratory Documents
The tentative labs and other ancillary documents are listed below. Lab assignments can change at any interval as well as their requirements. Check this or the daily calendar regularly.
Workings of lab and other items.
Guide from Digilent on what is on your Spartan 3E board including other interesting facts.
General Guidelines for Lab Report
Each group should hand in one report.
More in depth Guidelines for Lab Report
This document is how eventually your lab reports should end up before you are a senior. I would highly advise reading to get an idea of what to include when the time arises. I found, as a student, no one really told me what to include in a lab report well. Therefore, I created this document to help students.
Lab 1 - Introduction and Full Adder (2 weeks)
The primary objective of Lab 1 is to introduce you to the laboratory and prototyping. We will discuss digital logic and you will construct and verify the operation of a Full Adder circuit both with the Xilinx software and with 7400 parts.
Lab 1 Addendum - Workign with UCF files
Documents how to assign pins to their proper locations on your Spartan 3E boards.
Lab 2 - Seven Segment Display (2 weeks)
This lab discusses more complex combinational logic along with multi-output logic.
PreLab 2 Questions:
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Fill in Table 2
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Try to complete the K-map for each output in Table 2
Lab 2a - Ring Oscillators and Logic Analzyers (1 week)
This lab discusses what a logic analyzer is and how to use it.
Lab 3 - Adventure Game (2 weeks)
This lab introduces state machines with an introductory and simple adventure game.
PreLab 3 Questions:
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Complete Figure 3 as explained in the text.
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Draw a state transition table for each FSM.
Lab 4 - Tbird FSM (2 weeks)
This lab shows how state machines can be done with discrete and through the use of HDL.
Useful File: FSM Template File (fsm.v)
PreLab 4 Questions:
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Complete the state diagram, state transition table, and all of the next state logic and output logic including encodings.
Lab 5 - Arithmetic Logic Unit (2 weeks)
This lab shows how to design complex digital systems with Verilog HDL and testbenches.
PreLab 5 Questions:
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Complete Table 1
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Complex your Verilog HDL for your ALU 32
Project Part I - PacMan (™) (should be completed no later than November 12, 2009)
This project will show how to design complex digital systems and encompass all of your skills throughout the semester.
Ancillary Files:
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MIPS code (original code)
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MIPS code (added ori and bne instructions from PowerPoint lecture)
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mips.do (Simulation file for Mentor Graphics' ModelSim)
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wave.pdf (Output from mips.do documenting MIPS signals)
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MIPS Presentation - given in lab (ppt) (pdf) (pdfx6)
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Worksheets (Blank datapath/control for worksheets)
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temp2.asm - temp2.asm in Project Part 1 Definition
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temp2.asm - temp2.asm in Project Part 1 definition converted to binary
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temp2.out - temp2.asm output as displayed in instruction memory.
