Digital Logic Design
 

 

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Daily Calendar

The scheduled Topic and Laboratory calendar appears below. 

Course Week Dates Lectures

Assigned Text

Lab Assignment Comments
Week 1 8/18/09 Numbers, Two's Complement 1.1-1.4 Lab 1 (Intro)  
  8/20/09 Combinational Logic Introduction 1.5, 2.1    
Week 2 8/25/09 Combinational Logic Basics 2.2, 2.7 Lab 1 (Intro)  
  8/27/09 Working with K-maps 2.7  

Wikpedia

Week 3 9/1/09 K-maps and Don't Cares 2.4, 2.7 Lab 2 (7 Segment Lab)

Examples (sol)

  9/3/09 Schematics and more advanced K-maps with espresso/QM 2.4  

Simplified  K-map rules

Week 4 9/8/09 Boolean Algebra, Pushing Bubbles 2.3, 2.5 Lab 2a (Ring Oscillator Lab)

Handout on Boolean Algebra (tex)

  9/10/09 Multiplexors, Glitches, Delays, Synchronization with Clocks 2.8.1, 2.9    
Week 5 9/15/09 Introduction to Sequential Logic 3.1, 3.3 Lab 3 (Sequential Logic Lab)  
  9/17/09 Sequential Circuits, Finite State Machines, Moore Machines 3.4, 2.8.2    
Week 6 9/22/09 Mealy Machines, Differences between Moore and Mealy 3.4 Lab 3 (Sequential Logic Lab)  
  9/24/09 Bistable Elements, Memory, Latches, Flip-Flops 3.2    
Week 7 9/29/09 Test I   Lab 4 (Tbird Lights)  
  10/1/09 Introduction to Hardware Descriptive Languages, Testbenches 4.1, 4.4, 4.5 4.6    
Week 8 10/6/09 HDL basics and advanced features of simulation 4.2, 4.3

Lab 4 (Tbird Lights)

 
  10/8/09 Digital Building Blocks, Arithmetic Logic Unites, 5.1, 5.2      
Week 9 10/13/09 Sequential Building Blocks 5.4,5.6 Lab 5 (ALU Lab - Higher Level Combinational Logic with HDLs)  
  10/15/09 Logic Arrays, Field Programmable Gate Arrays (FPGAs) 5.5    
Week 10 10/20/09 Memory 5.6, 8.1 Lab 5 (ALU Lab - Higher Level Combinational Logic with HDLs)  
  10/22/09 Project Definition, Architecture handout    
Week 11 10/27/09 Instructions/Encoding 6.2, 5.3 Project Part I Demo
  10/29/09 Digital Video, Color Burst handout    
Week 12 11/3/09 Terminations Appendix A Project Part I  
  11/5/09 Combinational Logic Timing, Logic Families 2.8, 2.9    
Week 13 11/10/09 Sequential Logic Timing I 3.5 Project Part II  
  11/12/09 Test II      
Week 14 11/17/09 Sequential Logic Timing II, Setup and Hold delays, Measuring Setup/Hold. 3.5, 3.6 Project Part II  
  11/19/09 Setup/Hold Delays, Clock Skew handout    
Week 15 11/24/09 State Machine Optimization      
  11/26/09 Thanksgiving Holiday      
Week 16 12/1/09 Noise Margins, VTC, Levels 3.4.4 ECEN Design Day   
  12/3/09 Decomposition      
  12/4/09 Final Lab Report Due (no exceptions)      


 


This project is sponsored by the National Science Foundation under award NSF00311257.
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